Structure and fabricating method with self-aligned bit line contact to word line in split gate flash

ABSTRACT

A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates generally to semiconductorintegrated circuit technology and more particularly to split gate memorycells used in flash EPROMs (Electrically Erasable Programmable Read OnlyMemory).

[0003] (2) Description of Prior Art

[0004] Increased performance in computers is often directly related to ahigher level of circuit integration. Tolerances play an important rolein the ability to shrink dimensions on a chip. Self-alignment ofcomponents in a device serves to reduce tolerances and thus improve thepacking density of clips. Other techniques can be important in shrinkingdevice size. A method is disclosed later in the embodiments of thepresent invention of forming a structure with self-aligned bit linecontact to word line through which a significant reduction in the areaof the split gate flash cell is possible.

[0005] As is well known in the at, split gate flash cells have bit linesand word lines and bit contacts that connect bit lines to drain regions.Bit lines and bit contacts are insulated from the word lines by aninterlevel dielectric layer. The separation between bit contacts andword lines must be maintained large enough so as to avoid possibleshorts that could develop between adjacent bit contacts and word lines.Bit contact to word line separations are determined by the positions ofbit contact openings, which are set by a design rule. In arriving at thedesign rule the possibility of misalignment must be taken into account,which results in a required separation well beyond that needed to avoiddevelopment of shorts. This requirement for increased separation,arising from the need to account for unavoidable misalignment, limitsthe ability to decrease cell size. Self-alignment of the bit contact tothe word line, as in the structures disclosed by the present invention,eliminates the reliability issue, allows a reduction in cell area andfacilitates shrinking the cell size.

[0006] A traditional method of fabricating a split gate flash memorycell is presented in FIGS. 1a-1 g, where top views of the cell arepresented at successive stages of the process and in FIGS. 2a-2 g, whichshow the corresponding cross-sections. A floating gate oxide, 6, isformed on a semiconductor substrate, 2, which preferably is a siliconsubstrate, to a thickness of about 80 Angstroms, followed by depositionof a poly 1 layer, 8, to a depth of about 800 Angstroms. Active regions,10, are defined using isolating regions, such as shallow trenchisolation regions, 4. This is followed by deposition of a nitride layer,which preferably is a silicon nitride layer to a depth of about 2500Angstroms. A photoresist layer, 14, is then formed as shown in FIGS. 1band 2 b. The photoresist pattern, 14, is used in etching the siliconnitride layer to achieve the shape of region 12 of FIG. 2b. It isadvantages to perform a poly 1 etch so as to achieve the shape of region8 as shown in FIG. 2b. Details of the method to fabricate such sharppoly tips are presented in U.S. Pat. No. 6,090,668 to Lin et al., whichis herein incorporated by reference. Such sharp poly tips areadvantageous because they provide enhanced erase speed. Alter removal ofthe photoresist, an oxide 2 layer, 16, is deposited to a thickness ofabout 3000 Angstroms and a CMP (chemical-mechanical polishing) step isperformed. A second photoresist layer, 18, is formed and used insuccessively etching the silicon nitride layer and the poly 1 layer toachieve the structure shown in FIGS. 1c and 2 c. Source regions 20 areformed by a P ion implantation at energy of about 20 keV and to a doseof about 4E14 per cm2. Removal of the second photoresist layer isfollowed by deposition of an oxide 3 layer to a depth of about 500Angstroms, which enhances the lateral diffusion of the source implant.At oxide 3 etching step is performed to achieve oxide 3 spacers, 22. Apolysilicon deposition is performed to a depth of about 3000 Angstromsand a CPM step on this layer produces a poly 2 region 24, which servesto contact the source 20. At this stage the structure is as depicted inFIGS. 1d and 2 d. The traditional method proceeds with oxidation of poly2, 24, to form about 200 Angstroms of oxide 4, 26. Next the nitridelayer 12 is removed, and successive etches are performed of the poly 1layer, 8, and floating gate oxide 1 layer, 6. After a poly 3 deposition,30, to about 2000 Angstroms, the structure is as shown in FIGS. 1e and 2e. Etching the poly 3 layer, poly spacers, 30, are formed that serve asword lines. A drain implant is now performed that usually is an Asimplant at energy about 60 keV and to a dose of about 4E15 per cm2. Thisforms the drain regions 36. An interlevel dielectric (ILD) layer, 35 isdeposited. A photoresist layer is formed and patterned so that uponetching of the IDL layer, contacts are opened to the drain regions. Ametal 1 deposition follows removal of the photoresist layer. Anotherphotoresist layer is formed and patterned so that alter etching metal 1bit lines 34 are formed connecting to the drain regions, 36 through themetal 1 contact regions 32. This completes the formation of atraditional split gate flash cell, which is shown in FIGS. 1g and 2 g.

[0007] Bit lines, 34 and bit contacts, 32 are insulated from the wordlines, 30 by an interlevel dielectric layer, 38. The minimum separation,40, is between bit contacts and word lines and this separation must bemaintained large enough so as to avoid possible shorts that coulddevelop between adjacent bit contacts and word lines. Bit contact toword line separations are determined by the positions of bit contactopenings relative to word lines and the dimensions of the openings,which are set by design rules. In arriving at the design rule thepossibility of misalignment and variability in the production of contactopenings must be taken into account, which results in a required minimumseparation well beyond that needed to avoid development of shorts. Thisrequirement for increased separation limits the ability to decrease cellsize. Self-alignment of the bit contact to the word line, as in thestructures disclosed by the present invention, eliminates thereliability issue, allows a reduction in cell area and facilitatesshrinking the cell size.

[0008] A split-gate flash memory cell having self-aligned source andfloating gate self aligned to control gate, is disclosed in U.S. Pat.No. 6,228,695 to Hsieh et al. In U.S. Pat. No. 6,211,012 to Lee et al.there is disclosed an ETOX flash memory cell utilizing self alignedprocesses for forming source lines and landing pads to drain regions. InU.S. Pat. No. 5,479,591 to Lin et al. there is disclosed araised-bitline contactless flash memory cell. A method for fabricating asplit-gate EPROM cell utilizing stacked etch techniques is provided inU.S. Pat. No. 5,091,327 to Bergemont.

SUMMARY OF THE INVENTION

[0009] It is a primary objective of the invention to provide a splitgate flash cell with self-aligned bit contact to word line. It is also aprimary objective of the invention to provide a method of forming asplit gate flash cell with self-aligned bit contact to word line throughwhich a significant reduction in the split-gate flash cell area ispossible.** As is well known in the art a split-gate flash memory cellnormally has source and drain regions that are contacted by utilizingpoly plugs. Insulating layers are required as spacers to separate thesepoly plugs from the floating gates and control gates of the cell, andthis uses up area. Furthermore, because of the high voltages required inthe erase operation the spacer width cannot be decreased without payinga penalty in reduced reliability. Elimination of the poly plugs, as inthe method disclosed by the present invention, eliminates thereliability issue, allows a reduction in cell area and facilitatesshrinking the cell size. Instead of poly plugs, a new self-alignedsource/drain oxide etching procedure enables the formation ofsource/drain regions that are connected in rows directly within thesilicon. This procedure of collecting source/drains is generallyapplicable to arrays of MOSFET-like devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawing forming a material part of thisdescription, there is

[0011]FIGS. 1a-1 g show top views depicting a traditional method offorming split gate flash memory cells.

[0012]FIGS. 2a-2 g show cross sectional views depicting a traditionalmethod of forming split gate flash memory cells.

[0013]FIGS. 3a-3 j show top views depicting a method of forming splitgate flash memory cells according to the invention.

[0014]FIGS. 4a-4 j show cross sectional views depicting a method offorming split gate flash memory cells according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Preferred embodiments of the invention are well described withthe aid of FIGS. 3a-3 j and 4 a-4 j. A method of fabricating a novelsplit gate flash memory cell is presented in FIGS. 3a-6 j, where topviews of the cell are presented at successive stages of the process andin FIGS. 4a-4 j which show the corresponding cross-sections. A floatinggate oxide, 6, is formed on a semiconductor substrate, 2, whichpreferably is a silicon substrate, to a thickness of about 80 Angstroms,followed by deposition of a poly 1 layer, 8, to a depth of about 800Angstroms. Active regions, 10, are defined using isolating regions.,such as shallow trench isolation regions, 4. This is followed bydeposition of a nitride layer, which preferably is a silicon nitridelayer to a depth of about 2500 Angstroms. A photoresist layer, 4, isthen formed as shown in FIGS. 3b and 4 b. The photoresist pattern, 14,is used in etching the silicon nitride layer to achieve the shape ofregion 12 of FIG. 4b. A poly 1 etch is performed, and it is preferred toachieve the shape of region 8 as shown in FIG. 41) according to themethod described in U.S. Pat. No. 6,090,668 to Lin et al., which isherein incorporated by reference. Such sloped segments of the poly 1layer provide improved operation of the memory cell. After removal ofthe photoresist, an oxide 2 layer, 16, is deposited to a thickness ofabout 3000 Angstroms and a CMP (chemical-mechanical polishing) step isperformed. A second photoresist layer, 18, is formed and used insuccessively etching the silicon nitride layer and the poly 1 layer toachieve the structure shown in FIGS. 3c and 4 c. Source regions 20 areformed by a P ion implantation at energy of about 20 keV and to a doseof about 4E14 per cm2. Removal of the second photoresist layer isfollowed by deposition of an oxide 3 layer to a depth of about 500Angstroms, which enhances the lateral diffusion of the source implant.An oxide 3 etching step is performed to achieve oxide 3 spacers, 22. Apolysilicon deposition is performed to a depth of about 3000 Angstromsand a CPM step on this layer produces a poly 2 region 24, which servesto contact the source 20. At this stage the structure is as depicted inFIGS. 3d and 4 d. The method proceeds with oxidation of poly 2, region24, to form about 200 Angstroms of oxide 4, region 26. Next the nitridelayer 12 is removed, and successive etches are performed of the poly 1layer, 8, and floating gate oxide 1 layer. 6. After a poly 3 deposition,30, to about 2000 Angstroms, the structure is as shown in FIGS. 3e and 4e. At this point the method of the invention deviates from traditionalmethods. Instead of immediately performing an etch back step to formpoly 3 spacers 30, as in traditional methods, in which a rounded shaperesults, in the method of the invention a CMP process step is insertedbefore the poly 3 etch back. After the poly CMP step a more squareprofile is achieved for the poly 3, 42. As a result an essentiallyvertical profile is achieved for the poly 3 spacers 44, which are formedby etching hack the poly 3 region, 42. The oxide 5 layer remaining onthe drain area is now removed, which can be accomplished by a wet dipoxide etch or by an oxide dry etch. There follows an oxidation step inwhich oxide 6, 46, is grown to a thickness of about 600 Angstroms overthe exposed poly 3. An oxide of about half this thickness, 48, is grown,in this oxidation step, to the undoped silicon region in the drain area,so that the thickness of the oxide in that region is about 300Angstroms. Such a difference in thickness is due to the significantlyreduced oxide growth rate of undoped silicon substrate as compared todoped poly. The oxide growth rate of doped poly is about twice that ofundoped silicon. The difference in thickness of the oxides in regions 46and 48, a consequence of the difference in oxide growth rate, isimportant to the implementation of the invention. The next step is toform drain regions 52. This is preferably accomplished with an implantof As ions at energy of about 60 keV and to a dose of about 4E15 percm2. All oxide spacer etch follows in which all the oxide 48 over thedrain region is etched away, but oxide 6 layers over poly 3, 50 willremain, however at a reduced thickness of about 260 Angstroms. Theremaining oxide 6 layer serves as an insulating layer for the underlyingpoly 3 spacers, which act as word lines. A square profile is preferredsince more oxide remains, subsequent to the spacer oxide etch on theword line sidewalls for a square profile. This allows for the directdeposition of a poly 4 layer, which is performed to a depth of about2000 Angstroms. No intervening interlevel dielectric layer is required.Another photoresist layer is formed and patterned so that after etchingpoly 4, bit lines 54 are formed connecting to the drain regions, 52through the poly 4 contact regions 56. This completes the foliation of asplit gate flash cell according to the invention, which is shown inFIGS. 3j and 4 j.

[0016] Bit lines, 54 and bit contacts, 56 are insulated from the wordlines, 30 by an oxide 6 layer, 46 that was grown directly on the wordlines and is of a thickness sufficient to reliably insulate the wordlines from the bit lines and bit contacts. No area need be devoted toaccount for misalignment or imperfect accuracy in the dimension of theseregions. Self-alignment of the bit line and bit contact to the wordline, as in the structure of the present invention, eliminates thereliability issue, allows a reduction in cell area and facilitatesshrinking the cell size.

[0017] Other preferred embodiments of the invention are applicable tosituations where, in partially fabricated devices on a silicon substratethere are openings to a gate oxide layer disposed over the substrate.The openings are to contain a first conductive line disposed over theoxide and a contact region, connecting a second conductive line to thesilicon substrate that needs to be insulated from the first conductiveline. The second conductive line passes over the first conductive lineand needs to be insulated from the first conductive line. In the methodof the invention a first polysilicon layer is deposited to more thancover the openings. A CMP step is performed stopping at the top of theopenings. Etching back the first polysilicon layer follows to producepolysilicon spacers with essentially rectangular profiles over the gateoxide layer adjacent to the opening sidewalls and defining diminishedopenings to the gate oxide layer. All oxidation step is then performedthat results in an oxide layer grown over the exposed surfaces of thepolysilicon spacers. For a gate oxide layer about 170 Angstroms thickthe oxide over the polysilicon spacers should be grown to a thickness ofabout 600 Angstroms. Additional oxide is also grown during the oxidationstep, but to a lesser extent, under the exposed gate oxide layer in theopenings. The thickness of this layer is increased to about 340Angstrom, if the original gate oxide thickness was 170 Angstroms and 600Angstroms is grown on the polysilicon spacers. Only about 170 Angstromsis added mainly due to the significantly reduced oxide growth rate ofthe undoped silicon substrate as compared to doped polysilicon. Theoxide growth rate of doped poly is about twice that of undoped silicon.Also contributing to the relatively small increase in thickness is thatthe additional oxide is grown under the gate oxide layer that was thereprior to the oxidation step. Drain regions can now be formed itrequired. This is preferably accomplished with an implant of As ions atenergy of about 60 keV and to a dose of about 4E15 per cm2. A spaceroxide etch follows in which all the oxide over the silicon substrate ofthe openings is etched away, but an oxide layer will remain over thepolysilicon spacer, however at a reduced thickness of about 260Angstroms. This remaining oxide layer serves as an insulating layer forthe underlying polysilicon spacers. A deposition of a second polysiliconlayer follows, which is preferably performed to a depth of about 2000Angstroms. No intervening interlevel dielectric layer is required. Thesecond polysilicon layer filing the openings serve as contact regions. Aphotoresist layer is formed and patterned so that after etching thesecond polysilicon conductive lines are formed connected to the siliconsubstrate through the contact regions.

[0018] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetail may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A structure for semiconductor devices in whichcontact regions are self aligned to conductive lines, comprising: Asilicon substrate having thereon partially fabricated devices withopenings, first polysilicon lines disposed against insulating sidewallsof said openings in said partially fabricated devices on a siliconsubstrate, said first polysilicon lines extending from below the top ofthe openings to above said silicon substrate; oxide layers formed overthe top and sides of said first polysilicon lines that are not againstinsulating sidewalls of said openings and serving to insulate the firstpolysilicon lines; polysilicon contact regions disposed directly overand connecting to silicon substrate regions and Filling said openings;second polysilicon lines connecting to said contact regions and disposedover said oxide layers formed on said first polysilicon lines.
 2. Thestructure of claim 1 wherein said partially fabricated devices are splitgate flash cells. 3 The structure of claim 1 wherein said insulatingsidewalls are sidewalls of oxide regions.
 4. The structure of claim 1wherein said first polysilicon lines are spacers serving as word lines.5. The structure of claim 1 wherein said oxide layers grown on saidfirst polysilicon lines are greater than about 150 Angstroms thick. 6.The structure of claim 1 wherein said silicon substrate regionsconnecting to said contact regions are drain regions.
 7. The strictureof claim 1 wherein said second polysilicon lines are word linesconnecting to drain regions.
 8. A method of fabricating a structure forsemiconductor devices in which contact regions are self aligned toconductive lines, comprising: providing partially processed devices on asilicon substrate having openings with insulating sidewalls, saidopenings extending to a gate oxide layer on the silicon substrate;forming first polysilicon lines against the insulating side walls,extending from the top of said openings to said gate oxide layer on thesilicon substrate; growing an oxide layer on exposed sides of said firstpolysilicon lines whose thickness is greater than about three times thethickness of said gate oxide layer; implanting ions t-rough the gateoxide layer of the openings, that are not covered by said firstpolysilicon lines, to form device regions in the silicon substrate;performing an oxide etch sufficient to remove all the gate oxide layerof the openings, that are not covered by said first polysilicon lines,but leaving a thickness of oxide over said polysilicon lines that isgreater than the thickness of the gate oxide layer; forming contactregion-s by filling the remaining volume of said openings withpolysilicon; forming second polysilicon lines that are connected to saidcontact regions.
 9. The method of claim 8 wherein said partiallyfabricated devices are split gate flash cells.
 10. The method of claim 8wherein said insulating sidewalls are sidewalls of oxide regions. 11.The method of claim 8 wherein said first polysilicon lines are spacersserving as word lines.
 12. The method claim 8 wherein thickness of saidgate oxide layer is greater than about 150 Angstroms.
 13. The method ofclaim 8 wherein said device regions in the silicon substrate are drainregions.
 14. The method of claim 9 wherein said second polysilicon linesare word lines connecting to drain regions.
 15. The method of claim 8wherein said first polysilicon lines are formed by depositing a firstpolysilicon layer, performing CMP on said first polysilicon layer toreduce the layer to the top of said openings and performing a spaceretch back to produce first polysilicon lines, having rectangularcross-sections.
 16. The method of claim 8 wherein said implanted ionsare As ions implanted at energy of about 60 keV to a dose of about 4E15per cm2.
 17. The method of claim 8 wherein said contact regions andsecond polysilicon lines are formed by depositing a second polysiliconlayer, forming and patterning a photoresist layer and etching saidsecond polysilicon layer.
 18. A new structure for split gate flashmemories in which contact regions are self aligned to conductive lines,comprising: a silicon region extending to the surface of a semiconductorwafer with alternating parallel columns of source and drain regions;rows of device regions that are separated by isolation regions and areperpendicular to the source/drain columns, with polysilicon contactregions disposed over drain regions connecting the drain regions topolysilicon bit lines which mun in the row direction over the deviceregions, and said device regions as they are situated betweenconsecutive drain regions are, in order of occurrence: a spacer region,a floating gate region, a source line region, a floating gate region anda spacer region; spacer regions composed of polysilicon lines, whichserve as word lines in the column direction, that have oxide layers thatwere grown on the sides facing contact regions and on the top facing bitlines and oxide layers separating the spacer regions from the siliconregion and from the adjacent floating gate region; floating gate regionscomposed of a gate oxide layer over the silicon region that separatesthe silicon region from a polysilicon floating gate followed by an oxidelayer, giving a total height some what greater than the other deviceregions, and oxide spacers separate the floating gate regions fromadjacent source line regions; source line regions composed ofpolysilicon lines in the column direction that contact source regions atthe surface of the silicon region.
 19. The structure of claim 18 whereinsaid silicon region is p-type silicon.
 20. The structure of claim 18wherein said source and drain regions are n-type silicon regions. 21.The structure of claim 1 wherein said isolation regions are shallowtrench isolation regions.
 22. The structure of claim 18 wherein saidpolysilicon contact regions, polysilicon bit lines, polysilicon wordlines, polysilicon floating gates and polysilicon source lines are Pdoped to achieve high conductivity.
 23. The structure of claim 18wherein the grown oxide layers on said polysilicon word lines, on thesides of facing contact regions and on the top facing bit lines, arethicker than about 150 Angstroms.
 24. A method of fabricating a newstructure for split gate flash memories in which contact regions areself aligned to conductive lines, comprising: providing a siliconsubstrate and forming parallel alternating isolation regions and activeregions; forming a gate oxide-1 layer over said active regions; forminga doped poly-1 layer over said gate oxide-1 layer; forming a siliconnitride layer over said poly-1 layer; forming and patterning a firstphotoresist layer and etching said silicon nitride layer to form equallyspaced parallel, alternating wide and narrow silicon nitride sectionsperpendicular to the active regions; etching said poly-1 layer betweensaid silicon nitride sections to form sloped poly-1 profiles; removingsaid first photoresist layer; depositing an oxide-2 layer and performingCMP on this layer to the level of the silicon nitride sections; formingand patterning a second photoresist layer and sequentially etching thenarrow silicon nitride sections and the underlying poly-1 regions toexpose the underlying gate oxide-1 and creating narrow openings;performing a source ion implantation to form source regions under theexposed gate oxide-1; removing the second photoresist layer; forming anoxide-3 layer and etching said oxide-3 layer to form oxide-3 spacersalong d sidewalls; depositing a doped poly-2 layer and performing CMP toremove all poly-2 outside said narrow openings and creating poly-2source lines running perpendicular to the active regions and contactingthe source regions; forming oxide-4 caps over the tops of said poly-2source lines; performing a silicon nitride etch to remove the widesilicon nitride sections and creating wide openings; sequentiallyetching the poly-2 layer and oxide-layer from the bottoms of the wideopenings; forming an oxide-5 layer over exposed silicon and polysiliconsurfaces; forming a doped poly-3 layer- and perform CMP on said poly-3layer to the top of the oxide-2 layer; performing a poly-3 etch to formpoly-3 spacer regions that act as word lines running perpendicular tothe active regions; forming an oxide-6 layer over exposed surfaces ofpoly-3 spacer regions; performing a drain ion implantation to form drainregions under the exposed oxide-5; performing an oxide etch to removeexposed oxide-5 and underlying oxide formed during formation of saidoxide-6 layer but leaving an oxide-6 layer of reduced thickness oversaid poly-3 spacer regions; forming a doped poly-4 layer; forming andpatterning a third photoresist layer and etching said poly-4 layer toproduce poly-4 lines over said active regions that serve as bit lines.25. The method of claim 24 wherein said isolation regions are shallowtrench isolation regions.
 26. The method of claim 24 wherein saidsilicon substrate is a p-type silicon substrate.
 27. The method of claim24 wherein said gate oxide-1 layer is formed by growing an oxide to athickness of about 90 Angstroms.
 28. The method of claim 24 wherein saidpoly-1 layer is formed to a thickness of about 800 Angstroms.
 29. Themethod of claim 24 wherein said poly-1 layer is doped with phosphorus,either in situ or by ion implantation, to achieve high conductivity. 30.The method of claim 24 wherein said silicon nitride layer is formed to athickness of about 2500 Angstroms.
 31. The method of claim 24 whereinsaid oxide-2 layer is deposited to a thickness of about 2000 Angstroms.32. The method of claim 24 wherein said source ion implantation isperformed with P ions at energy of about 20 keV to a dose of about 4E14per cm2.
 33. The method of claim 24 wherein said oxide-3 layer isdeposited to a thickness of about 250 Angstroms.
 34. The method of claim24 wherein said poly-2 layer is formed to a thickness of about 800Angstroms.
 35. The method of claim 24 wherein said poly-2 layer is dopedwith phosphorus either in situ or by ion implantation, to achieve highconductivity.
 36. The method of claim 24 wherein said oxide-4 caps areformed by growing oxide layers on the tops of said poly-2 source linesto a thickness of about 200 Angstroms.
 37. The method of claim 24wherein said oxide-5 layer is grown to a thickness of about 170Angstroms over silicon surfaces.
 38. The method of claim 24 wherein saidpoly-3 layer is formed to a thickness of about 2000 Angstroms.
 39. Themethod of claim 24 wherein said poly-3 layer is doped with phosphorus,either in situ or by ion implantation, to achieve high conductivity. 40.The method of claim 24 wherein said oxide-6 layer is formed by growingan oxide layer to a depth of about 600 Angstroms over said exposedsurfaces of poly-3 spacers.
 41. The method of claim 24 wherein saiddrain ion implantation is performed with As ions at energy of about 60keV to a dose of about 4E15 per cm2.
 42. The method of claim 24 whereinsaid poly-4 layer is formed to a thickness of about 2000 Angstroms. 43.The method of claim 24 wherein said poly-4 layer is doped withphosphorus, either in situ or by ion implantation, to achieve highconductivity.